A known thin-film semiconductor device of this kind is shown in FIGS. 12 and 13, and consists mainly of a glass substrate a, a gate electrode G formed on the substrate a, a gate-insulating film b that covers the gate electrode G , a silicon semiconductor layer c formed on the gate-insulating film b, a channel-protecting film d for protecting the silicon semiconductor layer c, Ohmic contact layers e formed at both ends of the semiconductor layer c, a source electrode S and a drain electrode D deposited on the layers e, respectively, and conductive interconnects f connected with the source and drain electrodes S, D. The conductive interconnects f are made of aluminum (Al) or other similar material. The silicon semiconductor layer c is made of amorphous silicon (a-Si) and forms an active layer. The source and drain electrodes S, D are made of chromium or other material.
In this thin-film semiconductor device, a drain voltage V.sub.D is applied between the source electrode S and the drain electrode D. Also, a gate voltage V.sub.G is applied to the gate electrode G. Thus, a channel is formed in the silicon semiconductor layer c that is an active layer, and the device is turned on, permitting a drain current I.sub.D to flow. As the gate voltage V.sub.G is decreased, the channel ceases to be formed, so that the device is turned off. The device is typically incorporated in the head of an electrostatic plotter.
A high voltage must, therefore, be applied to the drain electrode D of this kind of thin-film semiconductor device, depending on the characteristics of the apparatus incorporating this semiconductor device. In the foregoing case, an electric discharge tends to take place between the source electrode S and the drain electrode D and between the gate electrode G and the drain electrode D, thus destroying the gate-insulating film b or the silicon semiconductor layer c.
Therefore, a thin-film semiconductor device designed to withstand high voltages has been developed. Specifically, as shown in FIGS. 14 and 15, in this semiconductor device, the gate electrode G is located close to the source electrode S that is at a low potential. An offset region g which does not proximately oppose the gate electrode G is formed in the silicon semiconductor layer c between the source electrode S and the drain electrode D. The gate electrode G is spaced relatively far from the drain electrode D which is at a high potential. In this way, destruction due to electric discharge is prevented.
In this thin-film semiconductor device designed to withstand high voltages, when the gate voltage V.sub.G is applied, a channel is formed in the silicon semiconductor layer c at a location opposite to the gate electrode G as shown in FIG. 15. Thereafter, carriers flow from the low potential source electrode S towards the interface with the gate-insulating film b. At the same time, the high potential drain electrode D sets up a strong electric field inside the offset region g. The carriers are pulled toward this electric field after passing through the channel, and then the carriers cross the potential barrier in the silicon semiconductor layer c and flow along the interface with a channel-protecting film d similar to the channel-protecting film d already described in connection with FIGS. 12 and 13. In this manner, this device serves the same function as the previously described semiconductor device.
Indeed this thin-film semiconductor device designed to withstand high voltages is excellent in that the silicon semiconductor layer c is prevented from being destroyed by electric discharge, but if an inverter circuit as shown in FIG. 16 is built using this semiconductor device, then the lower value V.sub.OL assumed by the output voltage V.sub.D from this inverter tends to become high. Hence, the characteristic of the inverter deteriorates.
More specifically, in the inverter circuit shown in FIG. 16, it is assumed that V.sub.S applied to the thin-film semiconductor device h designed to withstand high voltages is set to 0 V and that V.sub.HH applied to the drain is set to 500 V. It is also assumed that the gate input is driven by another transistor i. When the signal applied to the gate from the transistor i is at logic level 0, i.e., the gate voltage V.sub.G is off, then the thin-film semiconductor device h designed to withstand high voltages serves as a high resistor of about 10 G.OMEGA. and so the intended high output voltage V.sub.D of about 450 V is obtained from the inverter. On the other hand, when the signal applied to the gate from the transistor i is at logic level 1, i.e., the gate voltage V.sub.G is on, then the semiconductor device h conducts. At this time, the resistance is approximately 0.1 G.OMEGA.. Theoretically, the output voltage V.sub.D from the inverter is a low voltage of about 10 V. In practice, however, the semiconductor device does not fully conduct. Consequently, the lower output voltage V.sub.OL is higher than the above-described value.
Recently, a high voltage-withstanding thin-film semiconductor device free of this disadvantage has been developed. As shown in FIGS. 17 and 18, a field plate electrode j is formed to improve the conduction in the offset region g. In particular, this semiconductor device has the offset region g. The field plate electrode j is used to produce an electric field, is formed on an interlayer insulating film k above the end of the gate electrode G, and is located on the side of the offset region g. The energy of the electric field generated by the field plate electrode j is supplied to carriers passed through the channel so that the carriers may cross the potential barrier more easily to thereby improve conduction. The barrier is produced in the channel layer above the end of the gate electrode G that is located on the side of the offset region g. In consequence, an output voltage higher than the desired value is obtained. A device-protecting layer m, covers the whole device and is made of polyimide resin or the like.
In this, improved high-voltage withstanding semiconductor device, the field plate electrode j is formed on the interlayer insulating film k above the end of the gate electrode G that is located on the side of the offset region g as described above, into account the resistance to the high voltage applied to the field plate electrode j. This structure improves conduction, resulting in a lower output voltage V.sub.OL. The electrical insulation between the field plate electrode j and the silicon semiconductor layer c is provided by both channel-protecting film d and interlayer insulating film k and, therefore, if a small number of pinholes or cracks exist in the channel-protecting film d that is made of, for example, SiN.sub.x, sufficient resistance to high voltages can be secured.
On the other hand, the field plate electrode j is located remotely from the silicon semiconductor layer c, because the interlayer insulating film k and the channel-protecting film d are interposed between them. Therefore, the carriers passing through the channel cannot easily receive the energy from the electric field developed by the field plate electrode j. For example, in order to obtain a lower output voltage V.sub.OL of 10 V it is necessary to set the field plate electrode voltage V.sub.FP to a high value on the order of 100 V as illustrated by conventional example 2 shown in graph of FIG. 5. However, by increasing V.sub.FP the electric power consumed in the device is increased accordingly. In the thin-film, improved high-voltage withstanding manner, this semiconductor device suffers from a disadvantage.
Where the interlayer insulating film k is made of an organic material such as polyimide resin, the energy of the electric field developed by the field plate electrode j may not readily act on the carriers described above because of the polarization of the polyimide molecules themselves or the polarization of impurity ions or water molecules present in the polyimide resin. The value of the field plate electrode voltage V.sub.FP must, therefore, be increased accordingly. In addition, the polarization of the polyimide molecules themselves often varies with time. Concomitantly, the effective value of the field plate electrode voltage V.sub.FP changes. As a result, the lower output voltage V.sub.OL varies with time.
Where the interlayer insulating film k is made of an inorganic material such as SiO.sub.x or SiN.sub.x, the lower output voltage V.sub.OL varies less with time under the presence of polarization compared with the case in which the film k is made of an organic material such as polyimide resin. However, increased stress occurs between the channel-protecting film d and the insulating film k. For this reason, the effective value of the field plate electrode voltage V.sub.FP is liable to change. Hence, the lower output voltage V.sub.OL still varies with time.
If thin-film, improved, high-voltage withstanding semiconductor devices of this construction are integrated at a device density exceeding a certain value, then field plate electrodes j will be spaced quite close to adjacent source electrodes. Therefore, given the potential for short circuits between these electrodes, and production yield, and patterning accuracy, in addition to problems preventing intersections on the layout, conventional wisdom dictates that placing the aluminum interconnects f overlying the source electrode S and the drain electrode D together with the field plate electrode j is undesirable.
Under these circumstances, the conventional structure is that the source electrode S and the drain electrode D are brought out close to the thin-film semiconductor device designed to withstand high voltages. The aluminum interconnects f are disposed on the brought out electrodes S and D somewhat remote from the field plate electrode j. An apparatus in which the thin-film semiconductor devices designed to withstand high voltages are incorporated with a large device density shows good characteristics and production yield, but the drain electrode D made of chromium is eroded after prolonged operation of the apparatus.